Design and Application Guide of Bootstrap Circuit for High-Voltage

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AN-6076

Design and Application Guide of Bootstrap Circuit for

High-Voltage Gate-Drive IC

Rev. 1.4 • 12/18/14

www.fairchildsemi.com

1. Introduction

The purpose of this paper is to demonstrate a systematic

approach to design high-performance bootstrap gate drive

circuits for high-frequency, high-power, and high-efficiency

switching applications using a power MOSFET and IGBT.

It should be of interest to power electronics engineers at all

levels of experience. In the most of switching applications,

efficiency focuses on switching losses that are mainly depen-

dent on switching speed. Therefore, the switching character-

istics are very important in most of the high-power switching

applications presented in this paper. One of the most widely

used methods to supply power to the high-side gate drive cir-

cuitry of the high-voltage gate-drive IC is the bootstrap

power supply. This bootstrap power supply technique has the

advantage of being simple and low cost. However, it has

some limitations, on time of duty-cycle is limited by the

requirement to refresh the charge in the bootstrap capacitor

and serious problems occur when the negative voltage is pre-

sented at the source of the switching device. The most popu-

lar bootstrap circuit solutions are analyzed; including the

effects of parasitic elements, the bootstrap resistor, and

capacitor; on the charge of the floating supply application.

2. High-Speed Gate-Driver Circuitry

2.1 Bootstrap Gate-Drive Technique

The focus of this topic is the bootstrap gate-drive circuit

requirements of the power MOSFET and IGBT in various

switching-mode power-conversion applications. Where

input voltage levels prohibit the use of direct-gate drive cir-

cuits for high-side N-channel power MOSFET or IGBT, the

principle of bootstrap gate-drive technique can be consid-

ered. This method is utilized as a gate drive and accompany-

ing bias circuit, both referenced to the source of the main

switching device. Both the driver and bias circuit swing

between the two input voltage rails together with the source

of the device. However, the driver and its floating bias can

be implemented by low-voltage circuit elements since the

input voltage is never applied across their components. The

driver and the ground referenced control signal are linked by

a level shift circuit that must tolerate the high-voltage differ-

ence and considerable capacitive switching currents between

the floating high-side and ground-referenced low-side cir-

cuits. The high-voltage gate-drive ICs are differentiated by

unique level-shift design. To maintain high efficiency and

manageable power dissipation, the level-shifters should not

draw any current during the on-time of the main switch.

A widely used technique for these applications is called

pulsed latch level translators, shown in Figure 1.

Figure 1. Level-Shifter in High-Side Drive IC

2.2 Bootstrap Drive Circuit Operation

The bootstrap circuit is useful in a high-voltage gate driver

and operates as follows. When the V

goes below the IC

supply voltage V

or is pulled down to ground (the low-

side switch is turned on and the high-side switch is turned

off), the bootstrap capacitor, C

BOOT

, charges through the

bootstrap resistor, R

BOOT

, and bootstrap diode, D

BOOT

, from

the V

power supply, as shown in Figure 2. This is pro-

vided by V

when V

is pulled to a higher voltage by the

high-side switch, the V

supply floats and the bootstrap

diode reverses bias and blocks the rail voltage (the low-side

switch is turned off and high-side switch is turned on) from

the IC supply voltage, V

Figure 2. Bootstrap Power Supply Circuit

UVLO

PULSE GENERATOR

NOISE

CANCELLER

Shoot-through current

compensated gate driver

COM

DC SUPPLY

LOAD

RG2

RG1

BOOT

LOAD

BOOT

Bootstrap charge current path

Bootstrap discharge current path

AN-6076 APPLICATION NOTE

Rev. 1.4 • 12/18/14 2

2.3 Drawback of Bootstrap Circuitry

The bootstrap circuit has the advantage of being simple and

low cost, but has some limitations.

Duty-cycle and on time is limited by the requirement to

refresh the charge in the bootstrap capacitor, C

BOOT

The biggest difficulty with this circuit is that the negative

voltage present at the source of the switching device during

turn-off causes load current to suddenly flow in the low-side

freewheeling diode, as shown in Figure 3.

This negative voltage can be trouble for the gate driver’s out-

put stage because it directly affects the source V

pin of the

driver or PWM control IC and might pull some of the inter-

nal circuitry significantly below ground, as shown in Figure

4. The other problem caused by the negative voltage tran-

sient is the possibility to develop an over-voltage condition

across the bootstrap capacitor.

The bootstrap capacitor, C

BOOT

, is peak charged by the boot-

strap diode, D

BOOT

, from V

the power source.

Since the V

power source is referenced to ground, the

maximum voltage that can build on the bootstrap capacitor is

the sum of V

and the amplitude of the negative voltage at

the source terminal.

Figure 3. Half-Bridge Application Circuits

Figure 4. V

Waveforms During Turn-off

2.4 Cause of Negative Voltage on V

A well-known event that triggers V

go below COM

(ground) is the forward biasing of the low-side freewheeling

diode, as shown in Figure 5.

Major issues may appear during commutation, just before

the freewheeling diode starts clamping.

In this case, the inductive parasitic elements, LS1 and LS2,

may push V

below COM, more than as described above or

normal steady-state condition.

The amplitude of negative voltage is proportional to the par-

asitic inductances and the turn-off speed, di/dt, of the switch-

ing device; as determined by the gate drive resistor, R

GATE

and input capacitance, C

iss

, of switching device.

It is sum of C

and C

, called Miller capacitance.

Figure 5. Step-Down Converter Applications

Figure 6 shows the waveforms of the high-side, N-channel

MOSFET during turn-off.

Figure 6. Waveforms During Turn-off

LOCOM

DC SUPPLY

free

VDD

RG2

RG1

Ls1

Ls2

High Side OFF

Freewheeling Path

HIN

LIN

HIN

LIN

Load

BOOT

-V

HIN

Freewheeling

-COM

GND

INPUT

HVIC

BOOT

GATE

DRV

OUT

LOAD

Free

A B

GND

- V

OUT

GS,Miller

Recovery Time

A-Point

B-Point

C-Point

=B-C Point

AN-6076 APPLICATION NOTE

Rev. 1.4 • 12/18/14 3

2.5 Effects in the Undershoot Spike on V

If undershoot exceeds the absolute maximum rating speci-

fied in the datasheet, the gate drive IC suffers damage or the

high-side output is temporarily unresponsive to input transi-

tion as shown in Figure 7 and Figure 8.

Figure 7 shows Latch-up case that the high-side output does

not changed by input signal. In this case, short-circuit condi-

tion occur on external, main, high-side and low-side

switches in half-bridge topology.

Figure 7. Waveforms in Case of Latch-up

Figure 8 shows Missing case that the high-side output does

not responded to input transition. In this case, the level

shifter of the high-side gate driver suffers form a lack of the

operation voltage headroom. This should be noted, but

proves trivial in most applications, as the high-side in not

usually required to change state immediately following a

switching event.

Figure 8. Waveforms in Case of Signal Missing

2.6 Consideration of Latch-up Problem

The most integrated high-voltage gate-drive ICs have para-

sitic diodes, which, in forward or reverse break-down, may

cause parasitic SCR latch-up. The ultimate outcome of latch-

up often defies prediction and can range from temporary

erratic operation to total device failure. The gate-drive IC

may also be damaged indirectly by a chain of events follow-

ing initial overstress. For example, latch-up could conceiv-

ably result in both output drivers assuming a HIGH state,

causing cross-conduction followed by switch failure and,

finally, catastrophic damage to the gate-drive IC. This failure

mode should be considered a possible root-cause, if power

transistors and/or gate-drive IC are destroyed in the applica-

tion. The following theoretical extremes can be used to help

explain the relationships between excessive V

undershoot

and the resulting latch-up mechanism.

In the first case, an "ideal bootstrap circuit" is used in which

is driven from a zero-ohm supply with an ideal diode

feed V

, as shown in Figure 9. When the high current flow-

ing through freewheeling diode, V

voltage is below ground

level by high di/dt. This time, latch-up risk appears since

internal parasitic diode, D

of the gate driver ultimately

enters conduction from V

to V

, causing the undershoot

voltage to sum with V

, causing the bootstrap capacitor to

overcharge, as shown Figure 10.

For example, if V

=15 V, then V

undershoot in excess of

10V forces the floating supply above 25 V, risking break-

down in diode D

and subsequent latch-up.

Figure 9. Case 1: Ideal Bootstrap Circuits

Figure 10. V

and V

Waveforms of Case 1

INPUT

OUTPUT

Latch-Up Problem

INPUT

OUTPUT

Signal Missing Problem

COM

Gate Driver

GND

HIGH V

AN-6076 APPLICATION NOTE

Rev. 1.4 • 12/18/14 4

Suppose that the bootstrap supply is replaced with the ideal

floating supply, as shown in Figure 11, such that V

is fixed

under all circumstances. Note that using a low impedance

auxiliary supply in place of a bootstrap circuit can approach

this situation. This time, latch-up risk appears if V

under-

shoot exceeds the V

maximum specified in datasheet,

since parasitic diode D

BCOM

ultimately enters conduction

from COM to V

, as shown in Figure 12.

Figure 11. Case 2: Ideal Floating Supply

Figure 12. V

and V

Waveforms of Case 2

A practical circuit is likely to fall somewhere between these

two extremes, resulting in both a small increase of V

and

some V

droop below V

, as shown in Figure 13.

Figure 13. Typical Response of V

and V

Exactly which of the two extremes is prevalent can be

checked as follows. If the V

pins undershoot spike has a

time length that is on order of tenths of nanoseconds; the

bootstrap capacitor, C

BOOT

, can become overcharged and the

high-side gate-driver circuit has damage by over-voltage

stress because it exceeds an absolute maximum voltage

BSMAX

) specified in datasheet. Design to a bootstrap cir-

cuit, that does not exceed the absolute maximum rating of

high-side gate driver.

2.7 Effect of Parasitic Inductances

The amplitude of negative voltage is:

To reduce the slope of current flowing in the parasitic induc-

tances to minimize the derivative terms in Equation 1.

For example, if a 10 A, 25 V gate driver with 100nH para-

sitic inductance switches in 50 ns, the negative voltage spike

between V

and ground is 20 V.

3. Design Procedure of Bootstrap

Components

3.1 Select the Bootstrap Capacitor

The bootstrap capacitor (C

BOOT

) is charged every time the

low-side driver is on and the output pin is below the supply

voltage (V

) of the gate driver. The bootstrap capacitor is

discharged only when the high-side switch is turned on. This

bootstrap capacitor is the supply voltage (V

) for the high

circuit section. The first parameter to take into account is the

maximum voltage drop that we have to guarantee when the

high-side switch is in on state. The maximum allowable volt-

age drop (V

BOOT

) depends on the minimum gate drive volt-

age (for the high-side switch) to maintain. If V

GSMIN

is the

minimum gate-source voltage, the capacitor drop must be:

where:

= Supply voltage of gate driver [V]; and

= Bootstrap diode forward voltage drop [V]

The value of bootstrap capacitor is calculated by:

where Q

TOTAL

is the total amount of the charge supplied by

the capacitor.

The total charge supplied by the bootstrap capacitor is calcu-

lated by equation 4.:

where:

GATE

= Total gate charge;

LKGS

= Switch gate-source leakage current;

LKCAP

= Bootstrap capacitor leakage current;

QBS

= Bootstrap circuit quiescent current;

= Bootstrap circuit leakage current;

= Charge required by the internal level shifter, which is

set to 3 nC for all HV gate drivers;

= High-side switch on time; and

COM

Gate Driver

BCOM

GND

Below COM

GND

close to COM

Increased V

(1)

SSFDBOOTRBOOT

LLVVCOM )()(V

21S

+−+−=−

GSMINFDDBOOT

VVVV −−=Δ

(2)

BOOT

TOTAL

BOOT

(3)

LSONLKDIODELKQBSLKGSLKCAPGATETOTAL

QtIIIIIQQ +⋅+++++= )(

(4)

AN-6076 APPLICATION NOTE

Rev. 1.4 • 12/18/14 5

LKDIODED

= Bootstrap diode leakage current.

The capacitor leakage current is important only if an electro-

lytic capacitor is used; otherwise, this can be neglected.

For example: Evaluate the bootstrap capacitor value when

the external bootstrap diode used.

Gate Drive IC = FAN7382 (Fairchild)

Switching Device = FCP20N60 (Fairchild)

Bootstrap Diode = UF4007

= 15 V

GATE

= 98 nC (Maximum)

LKGS

= 100 nA (Maximum)

LKCAP

= 0 (Ceramic Capacitor)

QBS

= 120 µA (Maximum)

= 50 µA (Maximum)

= 3 nC

= 25 µs (Duty=50% at f

=20KHz)

LKDIODE

= 10 nA

If the maximum allowable voltage drop on the bootstrap

capacitor is 1.0V during the high side switch on state, the

minimum capacitor value is calculated by Equation 3.

The value of bootstrap capacitor is calculated as follows:

The voltage drop due to the external diode is nearly 0.7V.

Assume the capacitor charging time is equal to the high-side

on-time (duty cycle 50%). According to different bootstrap

capacitor values, the following equation applies:

Suggested values are within the range of 100 nF ~ 570 nF,

but the right value must be selected according to the applica-

tion in which the device is used. When the capacitor value is

too large, the bootstrap charging time slows and the low-side

on time might be not long enough to reach the bootstrap volt-

age.

3.2 Select the Bootstrap Resistor

When the external bootstrap resistor is used, the resistance,

BOOT

, introduces an additional voltage drop:

where:

CHARGE

= Bootstrap capacitor charging current;

BOOT

= Bootstrap resistance; and

CHARGE

= Bootstrap capacitor charging time (the low-side

turn-on time).

Do not exceed the ohms (typically 5~10 Ω) that increase the

time constant. This voltage drop of bootstrap diode

must be taken into account when the maximum allowable

voltage drop (V

BOOT

) is calculated. If this drop is too high or

the circuit topology does not allow a sufficient charging

time, a fast recovery or ultra-fast recovery diode can be used.

4. Consideration of Bootstrap

Application Circuits

4.1 Bootstrap Startup Circuit

The bootstrap circuit is useful in high-voltage gate driver, as

shown in Figure 1. However, it has a initial startup and lim-

ited charging a bootstrap capacitor problem when the source

of the main MOSFET (Q1) and the negative bias node of

bootstrap capacitor (C

BOOT

) are sitting at the output voltage.

Bootstrap diode (D

BOOT

) might be reverse biased at startup

and main MOSFET (Q1) has a insufficient turn-off time for

the bootstrap capacitor to maintain a required charge, as

shown in Figure 1.

In certain applications, like in battery chargers, the output

voltage might be present before input power is applied to the

converter. Delivering the initial charge to the bootstrap

capacitor (C

BOOT

) might not be possible, depending on the

potential difference between the supply voltage (V

) and

output voltage (V

OUT

) levels. Assuming there is enough

voltage differential between input voltage (V

) and output

voltage (V

OUT

), a circuit comprised of startup resistor

START

), startup diode (D

START

), and Zener diode (D

) can

solve the problem, as shown in Figure 14. In this startup cir-

cuit, startup diode D

START

serves as a second bootstrap

diode used for charging the bootstrap capacitor (C

BOOT

) at

power up. Bootstrap capacitor (C

BOOT

) is charged to the

Zener diode of D

, which is supposed to be higher than the

driver's supply voltage (V

) during normal operation. The

charge current of the bootstrap capacitor and the Zener cur-

rent are limited by the startup resistor. For best efficiency,

the value of startup resistor should be selected to limit the

current to a low value, since the bootstrap path through the

startup diode is permanently in the circuit.

][102.105

)103()}1025()1010

10501012010100{()1098(

969

6699

Total

−

−−−

−−−−

×=

×+×××+

×+×+×+×=

(6)

][105

102.105

BOOT

TOTAL

BOOT

≅

−

(7)

(8)

BOOT

TOTAL

BOOT

---------------------=

100nF V

BOOT

Δ 1.05 V=

150nF V

BOOT

Δ 0.7 V=

220nF V

BOOT

Δ 0.48 V=

570nF V

BOOT

Δ 0.18 V=

CHARGE

BOOTCHARGE

RBOOT

•

(5)

AN-6076 APPLICATION NOTE

Rev. 1.4 • 12/18/14 6

Figure 14. Simple Bootstrap Startup Circuit

4.2 Resistor in Series with Bootstrap Diode

In the first option, the bootstrap circuit includes a small

resistor, R

BOOT

, in series with bootstrap diode, as shown in

Figure 15. The bootstrap resistor, R

BOOT

, provides current

limit only during a bootstrap charging period which repre-

sents when the V

goes below the IC supply voltage, V

, or

is pulled down to ground (the low-side switch is turned on

and the high-side switch is turned off). The bootstrap capaci-

tor, C

BOOT

, charge through the bootstrap resistor, R

BOOT

and diode, D

BOOT

, from the V

power supply. The boot-

strap diode must have a break-down voltage (BV) larger than

and a fast recovery time to minimize the amount charge

feedback from the bootstrap capacitor to V

power supply.

Figure 15. Adding a Series Resistor with D

BOOT

This method has the advantage of being simple for limiting

the current when the bootstrap capacitor is initially charged,

but it has some limitations. Duty-cycle is limited by the

requirement to refresh the charge in the bootstrap capacitor,

BOOT

, and there are startup problems. Do not exceed the

ohms (typically 5~10 Ω) that would increase the V

time

constant. The minimum on-time for charging the bootstrap

capacitor or for refreshing its charge must be verified against

this time constant. The time constant depends on the values

of bootstrap resistance, capacitance, and duty cycle of

switching device calculated in following equation:

where R

BOOT

is the bootstrap resistor; C

BOOT

is the boot-

strap capacitor; and D is the duty cycle.

For example, if R

BOOT

=10, C

BOOT

=1 µF, and D=10 %; the

time constant is calculated in following equation:

Even with a reasonably large bootstrap capacitor and resis-

tor, the time constant may be large. This method can mitigate

the problem. Unfortunately, the series resistor does not pro-

vide a foolproof solution against an over voltage and it

slows down the recharge process of the bootstrap capacitor.

4.3 Resistor Between V

and V

OUT

In the second option, the bootstrap circuit includes a small

resistor, R

, between V

and V

OUT

, as shown in Figure 16.

Suggested values for R

are in the range of some ohms.

Figure 16. Adding R

in Bootstrap Circuit

The R

works as, not only bootstrap resistor, but also turn-

on and turn-off resistors, as shown in Figure 17. The boot-

strap resistor, turn-on, and turn-off resistors are calculated by

the following equations:

Figure 17. Current Paths of Turn-on and Turn-off

INPUT

BOOT

OUT

START

GATE

COM

HIN

BOOT

HIN

BOOT

HIN

COM

LIN

Load

(9)

BOOT

⋅

---------------------------------------- s[]=

(10)

BOOT

⋅

----------------------------------------

10 1

6–

⋅

0.1

------------------ 100 μs[]===

GND

HVIC

BOOT

GATE

DRV

OUT

BOOT

OUT

BOOT

∗

BOOT

(11)

∗

GATE

(12)

OFF

∗

GATE

(13)

GND

BOOT

GATE

DRV

OUT

BOOT

OUT

BCHG

TURN-ON

TURN-OFF

AN-6076 APPLICATION NOTE

Rev. 1.4 • 12/18/14 7

4.4 Clamping Diode for V

and Relocation

Gate Resistor

In the third option, the bootstrap relocates a gate resistor

between V

and V

OUT

and adds a low forward-voltage drop

Schottky diode from ground to V

, as shown in Figure 18.

The difference between V

and V

should be kept inside the

absolute maximum specification in the datasheet and must

be satisfied by the following equation:

Figure 18. Clamping Structure

4.5 Relocated Gate Resistor; Double Purpose

The gate resistor sets the turn-on and turn-off speeds in the

MOSFET and provides current limiting for the Schottky

diode during the negative voltage transient of the source ter-

minal of the main switch. In additional, the bootstrap capaci-

tor is protected against over voltage by the two diodes

connected to the ends of C

BOOT

. The only potential hazard

by this circuit is that the charging current of the bootstrap

capacitor must go through gate resistor. The time constant of

BOOT

and R

GATE

slows the recharge process, which might

be a limiting factor as the PWM duty cycle.

The fourth options includes relocating a gate resistor

between V

and V

OUT

and a clamp device should be posi-

tioned between ground and V

, as shown in Figure 19, where

a Zener diode and a 600 V diode are placed. The Zener volt-

age must be sized according to the following rule:

Figure 19. Clamping Structure with Zener Diode

5. Choose Current Capability HVIC

The approximate maximum gate charge Q

that can be

switched in the indicated time for each driver current rating

is calculated in Table 1:

Table 1. Example HVIC Current-Drive Capability

Note:

1. For a single 4 A, parallel the two channels of a dual 2 A!

For example, a switching time of 100 ns is:

1 % of the converter switching period at 100 KHz;

3 % of the converter switching period at 300 KHz; etc.

1. Needed gate driver current ratings depend on what gate

charge Q

must be moved in switching time t

SW-ON/OFF

(because average gate current during switching is I

2. The maximum gate charge, Q

, is read from the MOSFET

datasheet.

If the actual gate-drive voltage V

is different from the test

condition in the specifications table, use the V

vs. Q

curve instead. Multiply the datasheet value by the number

of MOSFETs in parallel.

3. t

SW_ON/OFF

is how fast the MOSFET should be switched.

If unknown, start with 2% of the switching period t

If channel (V-I) switching loss is dominated by one switch-

ing transition (turn-on or turn-off), size the driver for that

transition. For clamped inductive switching (the usual case),

channel switching loss for each transition is estimated as:

where V

and I

are maximum values during the switching

interval.

4. The approximate current drive capability of gate driver

may be calculated like below

(1) Sourcing Current Capability (Turn-on)

max_ absBSSB

VVV <−

(14)

GND

HVIC

BOOT

GATE

DRV

OUT

SCHT

OUT

(15)

–V

BS ABSMAX,

GND

HVIC

BOOT

GATE

DRV

OUT

Needed

Current

Rating

Switching Time (t

SW_ON/OFF

)

100 ns 50 ns

Maximum Gate Charge (Q

G,MAX

)

2 A 133 nC 67 nC

4 A 267 nC 133 nC

9 A 600 nC 300 nC

offonsw

SWAVG

(16)

(17)

SWON OFF,

0.02 t

0.02

-----------==

(18)

0.5V

× t

× Joules=

(19)

SOURCE

1.5

SW ON,

-------------------

×≥

AN-6076 APPLICATION NOTE

Rev. 1.4 • 12/18/14 8

(2) Sinking Current Capability (Turn-off)

where:

= MOSFET gate charge at V

= V

;

SW_ON/OFF

= MOSFET switch turn-on / turn-off time; and

1.5 = empirically determined factor (influenced by delay

through the driver input stages and parasitic elements).

6. Gate Resistor Design Procedure

The switching speed of the output transistor can be con-

trolled by values of turn-on and turn-off gate resistors con-

trolling the turn-on and turn-off current of gate driver. This

section describes basic rules for values of the gate resistors

to obtain the desired switching time and speed by introduc-

ing the equivalent output resistor of the gate driver. Figure

20 shows the equivalent circuit of gate driver and current

flow paths during the turn-on and turn-off, including a gate

driver and switching devices.

Figure 20. Gate Driver Equivalent Circuit

Figure 21 shows the gate-charge transfer characteristics of

switching device during turn-on and turn-off.

Figure 21. Gate Charge Transfer Characteristics

6.1 Sizing the Turn-On Gate Resistor

Turn-on gate resistor, R

g(ON)

, can be chosen to obtain the

desired switching time by using switching time, t

. To

determine a value of resistor using the switching time, sup-

ply voltage, V

(or V

), equivalent on resistance

DRV(ON)

) of the gate driver, and switching device parame-

ters (Q

, Q

, and V

gs(th)

) are needed.

The switching time is defined as the time spent to reach the

end of the plateau voltage (a total Q

+ Q

has been pro-

vided to the MOSFET gate), as shown in Figure 21.

The turn-on gate resistor calculated as follows:

where R

g(ON)

is the gate on resistance and R

DRV(ON)

is the

driver equivalent on resistance.

6.2 Output Voltage Slope

Turn-on gate resistor R

g(ON)

can be determined by control

output slope (dV

OUT

/dt). While the output voltage has a non-

linear behavior, the maximum output slope can be approxi-

mated by:

Inserting the expression yielding I

g(avr)

and rearranging:

where C

gd(off)

is the Miller effect capacitor, specified as C

rss

in the datasheet.

6.3 Sizing the Turn-Off Gate Resistor

The worst case in sizing the turn-off resistor is when the

drain of the MOSFET in turn-off state is forced to commu-

tate by external events.

In this case, dV/dt of the output node induces a parasitic cur-

rent through C

flowing in R

G(OFF)

and R

DRV(OFF)

, as

shown in Figure 22

The following describes how to size the turn-off resistor

when the output dv/dt is caused by the companion MOSFET

turning-on, as shown in Figure 22.

For this reason, the off-resistance must be sized according to

the application worst case. The following equation relates

the MOSFET gate threshold voltage to the drain dv/dt:

(20)

SINK

1.5

SW OFF,

----------------------

×≥

DRIVER

GND

DRIVER

GATE

Turn-On

Turn-Off

OFF

G(ON)

HVIC

OUT

G(OFF)

OUT

DRV(ON)

DRV(OFF

)

(21)

gavr()

-------------------------=

(22)

TOTAL

gON()

DRV ON()

gavr()

---------------------------==

(23)

OUT

------------------

gavr()

gd off()

-------------------=

(24)

TOTAL

gs th()

–

gd off()

OUT

------------------⋅

------------------------------------------=

AN-6076 APPLICATION NOTE

Rev. 1.4 • 12/18/14 9

Figure 22. Current Paths: Low-Side Switch Turned Off,

High-Side Switch Turned On

Rearranging the equation yields:

6.4 Design Example

Determine the turn-on and off gate resistors using the Fairch-

ild MOSFET with FCP20N60 and gate driver with

FAN7382. The power MOSFET of FCP20N60 parameters

are as follows:

=13.5 nC, Q

=36 nC, C

=95 pF, V

GS(th)

=5 V,

GS(th)MIN

=3 V

6.4.1 Turn-On Gate Resistance

1) If the desired switching time is 500 ns at V

=15 V, the

average gate charge current is calculated as:

The turn-on resistance value is about 58 Ω.

2) If dV

out

/dt=1 V/ns at V

=15 V, the total gate resistor is

as calculated as:

The turn-on resistance value is about 62 Ω.

7.4.2 Turn-Off Gate Resistance

If dV

out

/dt=1 V/ns, the turn-off gate resistor is calculated as:

8. Power Dissipation Considerations

8.1 Gate Driver Power Dissipation

The total power dissipation is the sum of the gate driver

losses and the bootstrap diode losses. The gate driver losses

are comprised of the static and dynamic losses related to the

switching frequency, output load capacitance on high- and

low-side drivers, and supply voltage, V

The static losses are due to the quiescent currents from the

voltage supplies V

and ground in low-side driver and the

leakage current in the level shifting stage in high-side driver,

which are dependent on the voltage supplied on the V

and proportional to the duty cycle when only the high-side

power device is turned on.

The dynamic losses are defined as follows: In the low-side

driver, the dynamic losses are due to two different sources.

One is due to whenever a load capacitor is charged or dis-

charged through a gate resistor, half of energy that goes into

the capacitance is dissipated in the resistor. The losses in the

gate drive resistance, internal and external to the gate driver,

and the switching loss of the internal CMOS circuitry. Also,

the dynamic losses of the high-side driver have two different

sources. One is due to the level-shifting circuit and one due

to the charging and discharging of the capacitance of the

high side. The static losses are neglected here because the

total IC power dissipation is mainly dynamic losses of gate

drive IC and can be estimated as:

Figure 23 shows the calculated gate driver power dissipation

versus frequency and load capacitance at V

=15 V. This

plot can be used to approximate the power losses due to the-

gate driver

DRIVER

GND

DRIVER

GATE

Turn-On

Turn-Off

OFF

G( ON)

HVIC

G( OFF)

DRV(ON)

DRV(OFF

)

OUT

LOAD

Load

CRR

iRRV

out

gddrvOFFg

gOFFDRVOFFgthgs

×+=

×+≥

){(

}){(

)()(

)()()(

(25)

)(

g(off)

drv

out

thgs

−

⋅

≤

(26)

][99

500

5.1336

)(

nCnC

gdgs

avrg

(27)

][101

515

)(

Ω=

−

mAI

avrg

thgsDD

Total

(28)

][43

350

)(

Ω≈==

SOURCE

ONDRV

(29)

][105

101095

515

912

)(

Ω=

××

−

⋅

−

OUT

offgd

thGSDD

Total

(30)

][43

350

)(

Ω≈==

SOURCE

ONDRV

(31)

][23

650

)(

Ω≈==

SINK

OFFDRV

(32)

6.823

101095

912

)(

min)(

g(off)

=−

××

=−

⋅

≤

−

drv

out

thgs

(33)

][2

WVfCP

DDsLDGATE

×××=

(34)

AN-6076 APPLICATION NOTE

Rev. 1.4 • 12/18/14 10

Figure 23. Gate Driver Total Power Dissipation

The bootstrap circuit power dissipation is the sum of the

bootstrap diode losses and the bootstrap resistor losses if any

exist. The bootstrap diode loss is the sum of the forward bias

power loss that occurs while charging the bootstrap capacitor

and the reverse bias power loss that occurs during reverse

recovery. Since each of these events happens once per cycle,

the diode power loss is proportional to switching frequency.

Larger capacitive loads require more current to recharge the

bootstrap capacitor, resulting in more losses.

Higher input voltages (V

) to the half-bridge result in

higher reverse recovery losses. The total IC power dissipa-

tion can be estimated by summing the gate driver losses with

the bootstrap diode losses, except bootstrap resistor losses.

If the bootstrap diode is within the gate driver, add an exter-

nal diode in parallel with the internal bootstrap diode

because the diode losses can be significant. The external

diode must be placed close to the gate driver to reduce para-

sitic series inductance and significantly lower forward volt-

age drop.

8.2 Package Thermal Resistance

The circuit designer must provide:

• Estimate power dissipation of gate driver package

• The maximum operating junction temperature T

MAX,OPR

, e.g., 120 °C for these drivers if derated to 80 %

of T

J,MAX

=150 °C.

• Maximum operating lead temperature T

L,MAX,OPR

approximately equal to the maximum PCB temperature

underneath the driver, e.g., 100 °C.

• Maximum allowable junction-to-lead thermal resistance

is calculated by:

9. General Guidelines

9.1 Printed Circuit Board Layout

The layout for minimized parasitic inductances is as follows:

• Direct tracks between switches with no loops or deviation.

• Avoid interconnect links. These can add significant

inductance.

• Reduce the effect of lead-inductance by lowering package

height above the PCB.

• Consider co-locating both power switches to reduce track

length.

• Placement and routing for decoupling capacitor and gate

resistors as close as possible to gate drive IC.

• The bootstrap diode as close as possible to bootstrap

capacitor.

9.2 Bootstrap Components

The bootstrap resistor (R

BOOT

) must be considered in sizing

the bootstrap resistance and the current developed during ini-

tial bootstrap charge. If the resistor is needed in series with

the bootstrap diode, verify that V

does not fall below COM

(ground), especially during startup and extremes of fre-

quency and duty cycle.

The bootstrap capacitor (C

BOOT

) uses a low-ESR capacitor,

such as ceramic capacitor. The capacitor from V

to COM

supports both the low-side driver and bootstrap recharge. A

value at least ten times higher than the bootstrap capacitor is

recommended.

The bootstrap diode must use a lower forward voltage drop

and switching time as soon as possible for fast recovery,

such as ultra-fast.

0.1 1 10 100 1000

0.01

0.1

Power [W]

Switching frequency [kHz]

LOAD

=4400PF

LOAD

=470PF

LOAD

=1000PF

LOAD

=2200PF

At V

= 15V

PKG

max,max,

max,

−

(35)

AN-6076 APPLICATION NOTE

Rev. 1.4 • 12/18/14 11

Table 2. Summary of High-Side Gate Drive Circuitry

Method Basic Circuit Advantages & Limitations

High-Side Gate Drivers for P-Channel

Direct Drive

Can be implemented if the maximum input voltage is

less than the gate-to-source break down voltage of

the device.

Open Collector

Simple method, but is not suitable for driving

MOSFET directly in a high-speed application.

Level-Shifted Drive

Suitable for high-speed application and works

seamlessly with regular PWM controller.

High-Side Gate Drivers for N-Channel

Direct Drive

Easiest high-side application the MOSFEF and can

be driven directly by the PWM controller or by a

ground referenced driver, but it must meet two

conditions, as follows:

Floating Supply

Gate Drive

Cost impact of isolated supply is significant. Opto-

coupler tends to be relatively expensive, limited in

bandwidth, and noise sensitive.

Transformer

Coupled Drive

Gives full gate control for an indefinite period of time,

but is somewhat limited in switching performance.

This can be improved with added complexity.

Charge Pump

Drive

The turn-on times tend to be long for switching

applications. Inefficiencies in the voltage

multiplication circuit may require more than low

stages of pumping.

Bootstrap Drive

Simple and inexpensive with limitations; such as,

the duty cycle and on-time are both constrained by

the need to refresh the bootstrap capacitor.

Requires level shift, with the associated difficulties.

PWM

Controller

GATE

OUT

GND

OUT

GND

PWM

Controller

GATE

OUT

PULL

PWM

Controller

BASE

OUT

GATE

GND

OUT

INV

PWM

Controller

GATE

OUT

GND

OUT

SCHT

MillerGSCCDCMAXGSCC

VVVandVV

−<<

PWM

Controller

GATE

OUT

GATE

GND

Floating

Supply

Opto

PWM

Controller

GATE

OUT

GATE

BLOCK

GND

OUT2

OUT1

GND

PWM

Controller

OUT

GND

HVIC

BOOT

GATE

DRV

OUT

AN-6076 APPLICATION NOTE

Rev. 1.4 • 12/18/14 12

Consideration Points of Bootstrap Circuit Problem

Remedies of Bootstrap Circuit Problem

GND

INPUT

HVIC

BOOT

GATE

DRV

OUT

The amplitude of the negative voltage is proportional

parasitic inductances and the turn-off speed (di/dt) of

the switching device, Q1, which is determined by gate

resistor, R

GATE

, and input capacitance, C

iss

Latch-up,

propagation signal

missing and over-

voltage across the

bootstrap

capactor

If V

goes significantly below

ground, the gate driver can

have serious troubles.

Negative voltage transient

at high-side switch turn-off.

GS,Miller

Recovery Time

A-Point

B-Point

C-Point

=B-C Point

LOAD

Free

A B

GND

- V

= (V

-V

FBD

) - (-V

)

AN-6076 APPLICATION NOTE

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Rev. 1.4 • 12/18/14 13

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